The increased usage of analog to digital converters (ADC's) within a variety of applications has provided an impetus for the development of inexpensive ADC's capable of relatively high-performance. Conventional "single conversion cycle flash" ADC's (also called "full-flash" ADC's) have generally been found to offer insufficient performance, and are often too costly for use in inexpensive consumer products. In particular, conventional flash converters include an array of 2.sup.N -1 comparators for comparing an analog input signal to a number of threshold reference voltages, where N is the number of output bits in the digital value generated by the ADC. The comparators are assumed to provide a logical ONE when the output of a comparator exceeds its threshold, and a logical ZERO otherwise. An array of latches determines the logical state of the comparators during each clock cycle and holds this information until sampling during the succeeding cycle. The outputs of each latch are then encoded into an output code. Among the disadvantages of the full-flash implementation are high power consumption, large chip area, as well as the requirements for numerous components and interconnection lines.
Two-conversion cycle flash ADCs and multiple-conversion cycle flash ADCs reduce the number of comparators needed by generating a subset of the output bits during each conversion cycle, but sacrifice speed. Such devices, with a typical conversion rate of one input sample per microsecond, are much too slow for medical imaging systems and other applications that require data conversion rates of 10 Megahertz or faster.
One method of decreasing the number of components required within an ADC, without requiring multiple conversion cycles, is effected through a technique commonly known as "folding". This technique reduces the size of the flash array necessary to implement a converter of a given precision by using the flash array (i.e., comparison circuits) in a more efficient manner. Specifically, in ADC's based on a folding architecture an analog processing circuit, a first flash array and decoder generate the most significant bits (MSBs) of the output value, while a "folder circuit" precedes a second flash array. The folder circuit effectively "subtracts" from the input signal the amount of voltage represented by the MSBs, leaving a remainder voltage that precisely corresponds to the least significant bits (LSBs) of the output value.
1 LSB is defined as the voltage step associated with the least significant bit of the ADC conversion value. In a 10-bit ADC, having an input voltage range of 2 volts, 1 LSB is 1.953125 millivolts.
Referring to FIG. 1A, there is shown a block diagram of a conventional 10-Bit folding analog to digital converter 100 incorporating a 5-Bit folder circuit 102. During each sampling period an analog input signal is sampled by an input sample and hold circuit 105 and applied to the 5-bit folder circuit 102 and to a conventional 5-bit MSB flash array 106.
FIG. 1B shows the ideal transfer function of the 5-bit folder circuit 102. The magnitude of the analog output of the folder circuit 102 is indicative of the value of the five least significant bits of the sampled analog input. That is, the folder circuit output corresponds to a residual portion of the sampled analog input in excess of the voltage magnitude equivalent to the first five MSB's of the sampled analog input.
A digital code corresponding to the five MSB's of the analog input is produced by the 5-bit MSB flash array 106 in conjunction with an MSB decoder 108 that generates the actual five MSB's. The MSB flash array 106 compares the sampled input voltage with a first set of thirty-one reference voltages (which are spaced at 32 LSB intervals) from a voltage reference ladder 104, producing a 32-level "thermometer" code. The MSB decoder 108 converts that 32-level "thermometer" code into a 5-bit value.
Similarly, a second 32-level "thermometer" code is generated by a 5-bit LSB flash circuit 110, by comparing the output of the folder circuit 102 with a second set of thirty-one reference voltages (which are spaced at 1 LSB intervals) from a voltage reference ladder 104. The second thermometer code is transformed into a binary code by an LSB decoder 112 to yield the five LSBs of the analog input.
It should be noted that the reference voltages used in typical MSB and LSB flash arrays are offset by -0.5 LSB from their nominal values. The reason for the half LSB offset is that the standard specification for ADC circuits is that the digital output value should shift from one value to the next when the input voltage passes the halfway point between the two. For instance, the digital output value of the ADC switches from 0 to 1 when the input voltage Vin rises above 0.5 LSB.
As can be seen from the voltage transfer function shown in FIG. 1B, when the output voltage of the folder circuit 102 is on a positively sloped portion of its transfer function, the LSB decoder must generate a digital value that increases as the folder circuit output voltage increases. However, when the output voltage of the folder circuit is on a negatively sloped portion of its transfer function, the LSB decoder must generate a digital value that increases as the folder circuit output voltage decreases. Thus, the five LSBs to be generated by the ADC may be uniquely determined by the LSB decoder 112 only after it is known whether the output of the folder circuit 102 was based upon one of the positively-sloped or upon one of the negatively-sloped portions of the folder transfer characteristic. This information is inherent within the value of the lowest MSB, and is provided to the LSB decoder 112 by the MSB decoder 108. The requirement that the LSB decoder 112 be provided with information from the MSB decoder 108 tends to reduce the efficiency of the ADC 100, since the LSB decoder 112 is idle pending completion of the MSB flash operation.
It is noted that in MOS implementations of sample and hold circuits the analog input is applied to the source terminal of an input sampling transistor, and is allowed to pass therethrough during each clock cycle. The magnitude of the sampled analog signal is stored by a capacitor connected to the output (drain) terminal of the sampling transistor. This type of sample and hold circuit may be modeled as an RC circuit, where R is primarily determined by the channel resistance of the input transistor and where C corresponds to the capacitance value of the "holding" capacitor. Since the bias applied to the gate of the sampling transistor is a constant and the value of R depends on the gate to source voltage of the sampling transistor, the value of R varies as a function of the magnitude of the input voltage. Hence, harmonic distortion is introduced into the sampled input signal as a consequence of variation in the RC time constant of the sample and hold circuit.
The performance of the analog to digital converter 100 depends largely upon:
(1) the degree to which the folding function depicted in FIG. 1B may be accurately implemented by the folder circuit 102, PA1 (2) accurate or consistent sampling of the input signal, PA1 (3) the precision of the reference voltages provided by the reference ladder 104, and PA1 (4) the speed of the folder circuit 102.
Each of these factors, other than the consistent sampling factor which was discussed above, are discussed next with reference to the diagram of a conventional folding circuit 102 shown in FIG. 2. Note that it is assumed in this circuit that the analog input voltage range is -2 volts to 0 volts.
Conventional folding circuits have been shown to introduce distortion into the ideal transfer characteristic of FIG. 1B. Referring to FIG. 2, the accuracy of the gain of the folder circuit 102 is dependent upon the ratio of the pull-up resistors R1, R2 and R3 (which ideally should all be precisely equal) to the current drawn by current sources I. However, the gain may be affected by contributions from the base currents of transistors T1-T4. Thus, non-uniformities in the current sources and pull-up resistors and base currents in the folder circuit's transistors all contribute to deviation in the gain of the folder circuit 102 from a specified ideal absolute value.
As is indicated by FIG. 1B, the folding circuit 102 is characterized by a piece-wise linear transfer characteristic. Such linearity has proven difficult to achieve in practice, however, due to the hyperbolic tangent transfer characteristic of the differential transistor pairs T1-T2, T3-T4, only two of which are shown in FIG. 2. Efforts directed to improving the linearity of these differential pairs have involved connecting resistors to the emitter of the transistors within each differential pair. While this has led to improved linearity, it has also tended to reduce circuit gain and requires the matching of an additional pair of resistors.
Referring to FIG. 1B and to FIG. 2, when the sampled analog input is near the m.sup.th multiple of the reference voltage V.sub.R the current from current source I1 is split primarily between transistors TRm and TR(m+1). This results in a reduction of the base-emitter voltage drop through these transistors relative to the case in which current flow is predominantly through only one of the transistors TR. It follows that the actual output voltage of the folder circuit 102 tends to be higher than desired in response to analog inputs which are proximate multiples of the reference voltage V.sub.R. The non-linearity introduced into the transfer characteristic of the folder 102 as a consequence of this effect is depicted in FIG. 3, in which the folder output voltage at room temperature is shown to be offset by approximately 18 mV from the desired output voltage for analog inputs near multiples of the reference voltage V.sub.R.
As may also be appreciated with reference to FIG. 3, the voltage at node N2 of the folder circuit 102 (FIG. 2) varies between VN2, max and VN2, min as a function of the sampled analog input. Referring to FIG. 2, the peak output voltage of the folder circuit 102 is one base-emitter threshold (VBE) below the maximum voltages impressed upon the nodes N1, N2, . . . Nn. The maximum voltage at the nodes N1, N2, . . . , Nn occurs for analog inputs having magnitudes midway between adjacent reference voltages and cannot exceed-Vupper, where Vupper is the voltage drop across resistors R1, R2, . . . Rn, when the current drawn through each such resistor is at its minimum level.
With reference to FIG. 2, the speed of the conventional folder 102 can be degraded by saturation effects precipitated by relatively large analog input voltages. In particular, when the analog signal applied to the input transistor of a differential pair becomes large compared with the associated reference voltage the input transistor tends to be driven into saturation, i.e., the collector voltage exceeds the saturation threshold. Saturation of the input transistors within a differential pair reduces the rate at which the associated folder stage is capable of responding to changes in the sampled analog input.
Efforts have also been made to enhance the precision of the reference voltages supplied to the flash arrays and folder circuits included within high-speed ADC's. For example, ADC's designed to be incorporated within high-speed video processing systems often include low-impedance voltage reference ladders for providing a set of reference voltages. Referring to the conventional reference ladder shown in FIG. 4, a resistive diffusion or metallic interconnection line R.sub.D is operatively connected to positive (+V1) and negative (-V2) force voltages supplied by a force and sense circuit. The force and sense circuit is employed to set the voltage at sense terminals S1 and S2 at either end of the resistive line R.sub.D to the reference potentials MinV.sub.R and MaxV.sub.R. Specifically, the force and sense circuit includes a feedback network which adjusts the magnitude of +V1 and -V2 so that MinV.sub.R and MaxV.sub.R are applied to the resistive line R.sub.D despite the presence of parasitic interconnection resistance Rp. In this way the magnitude of the reference potentials are made to be relatively independent of the magnitude of Rp. Since the resistive line RD is assumed to be of uniform width, the tap points corresponding to each reference potential may be determined through linear interpolation.
In many analog to digital converters the reference potentials MinV.sub.R and MaxV.sub.R correspond to the zero and full-scale values used during the conversion process. Nonetheless, certain high-speed ADC's include folding circuits which require internal voltage references which are several LSBs beyond these zero and full-scale values. Simply increasing the dynamic range between the zero and full-scale values to include these additional reference voltages has been considered, but would lead to unusual values for the zero and full-scale references. This would, in turn, complicate the interpolation process used to select the tap points corresponding to the remaining reference values.
Referring to FIG. 5, the actual relationship between the locations of tap points along the resistive line RD and the corresponding reference voltages (solid line) is seen to be nonlinear when current is drawn from the tap points, such as to provide the base current of NPNs in the ADC's folder circuits and in the ADC's flash arrays. The resulting error between the ideal linear interpolation characteristic (dashed line) and that actually obtained can lead to significant error in the reference voltages derived from tap points proximate the center of the resistive line RD.
Because operation of the folder circuit 102 is predicated upon the absolute gain and linearity of its constituent circuit elements, its output is relatively sensitive to variation in temperature. Accordingly, it has generally been necessary to develop performance specifications based on limited temperature ranges.